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XR-T6166
...the analog plus company TM
Codirectional Digital Data Processor
June 1997-3
FEATURES D Low Power CMOS Technology D All Receiver and Transmitter Inputs and Outputs are TTL Compatible D Transmitter Inhibits Bipolar Violation Insertion for Transmission of Alarm Conditions D Alarm Output Indicates Loss of Received Bipolar Violations D Tolerance of 125s Variance of Data Transfer Timing in Both Transmit and Receive Paths Allows Operation in Plesiochronous Networks D Both Receiver and Transmitter Perform Byte Insertion or Deletion in Response to Local Clock Slips and Provide Outputs Indicating Slip Logic Activity
APPLICATIONS D CCITT G.703 Compliant 64kbps Codirectional Interface D Performs the Digital and Analog Functions for a Complete 64kbps Data Adaption Unit (DAU) When Used With the XR-T6164
GENERAL DESCRIPTION The XR-T6166 is a CMOS device which contains the digital circuitry necessary to interface both directions of a 64kbps data stream to 2.048Mbps transmit and receive PCM time-slots. The XR-T6166 and the companion XR-T6164 line interface chip together form a CCITT G.703 compliant 64kbps codirectional interface. The XR-T6166 contains separate transmit and receive sections. The transmitter transforms 8 bit serial data from a 2.048Mbps time-slot into an encoded 64kbps data ORDERING INFORMATION Operating Temperature Range
0C to +70C -40C to 85C 0C to +70C -40C to 85C
stream. The receiver, which performs the reverse operation, decodes the 64kbps data, extracts a clock signal, and then outputs the data to a 2.048Mbps time-slot. The XR-T6166 provides features which allow the repetitions and deletions of both received and transmitted data as clock skews and transients occur. These slip occurrences are indicated by byte insertion and deletion flags. Outputs are also provided for extracted receive clock and clock recovery circuit loss of lock.
Part No.
XR-T6166CP XR-T6166IP XR-T6166CD XR-T6166ID
Package
28 Lead 600 Mil PDIP 28 Lead 600 Mil PDIP 28 Lead 300 Mil JEDEC SOIC 28 Lead 300 Mil JEDEC SOIC
Rev. 2.02
E1990
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7010 1
XR-T6166
PCMIN TX2MHz TS1T TS2T TTSEL
19
D
20
8 Bit Input Register CLK 8 Byte Deletion
10
11
BDT
12
time-slot Mux
8 Bit Latch Load 8 CLK 8 Bit Output Register Load Q Byte Insertion
18
15
BIT
Control Circuitry TX256kHz
17
Octet Counter
Violation Insertion
Coding Logic
D CLK Q D CLK Q
13
T+R
ALARMIN
16
14
T-R
Figure 1. XR-T6166 Transmitter Section Block Diagram
Byte Sync Detection CLK S+R S-R
2
Violation Loss Alarm Data Decoder CLK
1
ALARM
3
BLS
4
D RX2MHz TS1R TS2R RTSEL
5
Q
28
23
time-slot Mux Time Slot Mux
Register Select Logic
8 Bit Reg 0 CLK D Q 8 Bit Reg 1 CLK REG 0 SEL REG 1 SEL time-slot
PCMOUT
24
27
Byte Insertion
26
BIR
BLANK
6
Byte Deletion 128kHz Recovered Clock
25
BDR
RXCK2MHz
9
Clock Recovery
7
RXCKOUT CS
22
Figure 2. XR-T6166 Receiver Section Block Diagram
Rev. 2.02 2
XR-T6166
PIN CONFIGURATION
ALARM S+R S-R BLS RX2MHz BLANK RXCKOUT VDD RXCK2MHz TS1T BDT TS2T T+R T-R
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PCMOUT RTSEL BIR BDR TS2R TS1R CS VSS TX2MHz PCMIN BIT TX256kHz ALARMIN TTSEL
ALARM S+R S-R BLS RX2MHz BLANK RXCKOUT VDD RXCK2MHz TS1T BDT TS2T T+R T-R
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PCMOUT RTSEL BIR BDR TS2R TS1R CS VSS TX2MHz PCMIN BIT TX256kHz ALARMIN TTSEL
28 Lead PDIP (0.600")
28 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol ALARM S+R S-R BLS RX2MHz BLANK RXCKOUT VDD RXCK2MHz TS1T BDT TS2T T+R T-R TTSEL ALARMIN I I O I O O I I Type O I I I I I O Description Octet Timing Alarm. When active, indicates loss of received bipolar violations that are used for octet timing. Active high. Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side. Active low. Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side. Active low. Byte Locking Supervision. When active, causes blanking of PCMOUT under received alarm conditions. Active low. Receiver 2.048MHz Clock. Used to clock out PCM data. PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS). Active high. 128kHz Extracted Clock. Clock recovered from received data. +5V $10% Power Source. 2.048MHz Clock. Used by receiver clock recovery circuit. Transmitter Time-slot 1 Input. Transmitter Byte Deletion Flag. Active when a transmit byte is deleted. Active high. Transmitter Time-slot 2 Input. Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input. Active low. Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input. Active low. Transmit Time-slot Select. When high, pin 10 is selected; when low, pin 12 is selected. Alarm Input. When active, inhibits insertion of violations used for octet timing in transmitter output. Active high.
Rev. 2.02 3
XR-T6166
PIN DESCRIPTION (CONT'D)
Pin # 17 18 19 20 21 22 23 24 25 26 27 28 Symbol TX256kHz BIT PCMIN TX2MHz VSS CS TS1R TS2R BDR BIR RTSEL PCMOUT O I I O O I O Type I O I I Description Transmitter 256kHz Clock. Used to output 64kbps encoded data. Transmitter Byte Insertion Flag. Active when a transmit byte is repeated. Active high. Transmitter PCM Input. Data read from the system PCM bus. Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN. Ground. Clock Seek. Indicates that clock recovery circuit has loss of lock with received data. Active high. Receiver Time-slot 1 Input. Receiver Time-slot 2 Input. Receiver Byte Deletion Flag. Active when received data byte is deleted. Active high. Receiver Byte Insertion Flag. Active when a received data byte is repeated. Active high. Receive Time-slot Select. When high, pin 23 is selected; when low, pin 24 is selected. Received PCM Output Data. Data sent to the system PCM bus.
Rev. 2.02 4
XR-T6166
ELECTRICAL CHARACTERISTICS Test Conditions: VDD = 5V $10%, TA = 25C, Unless Otherwise Specified
Symbol Parameter Min. Typ. Max. Unit Conditions
DC Electrical Characteristics VIH VIL VDD IDD IIL VOL VOH AC Electrical Characteristics General tr, tf Receiver tRS tRH tDRS tDRH tRXD RX2MHz Rising Edge to TS Rising Edge Set Up Time RX2MHz Rising Edge to TS Falling Edge Hold Time TS Rising Edge to Leading Edge of PCMOUT D0 Bit Delay TS Falling Edge to Trailing Edge of PCMOUT D7 Bit Hold Time RX2MHz Rising Egde to PCMOUT Bits D1 Through D6 Rising Edge Delay PCMOUT Pulse Width RX2MHz High Time RX2MHz Low Time RX2MHz Period 488 244 244 488 0 0 0 tRXL100 tRXL100 10 10 10 ns ns ns ns ns Output Rise/Fall Time 20 ns All Outputs 2.4 Logic 1 Logic 0 Supply Supply Current Input Leakage 4.5 500 1 0.4 2.4 0.4 5.5 V V V A A V mA At 1.6mA At 0.4mA Dynamic Supply Current
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
tPW tRXH tRXL tRXCLK Transmitter tTS tTH tDS tDH tTXH tTXL tTXCLK Rev. 2.02
ns ns ns ns
Figure 3 Figure 3 Figure 3
$100ppm
TS Rising Edge to TX2MHz Set Up Time TS Falling Edge to TX2MHz Hold Time PCMIN Edge to TX2MHz Set Up Time PCMIN Edge to TX2MHz Hold Time TX2MHz High Time TX2MHz Low Time TX2MHz Period
20 0 100 100 244 244 488
tTXL100 tTXL100
ns ns ns ns ns ns ns
Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5
$100ppm
5
XR-T6166
ELECTRICAL CHARACTERISTICS (CONT'D)
Symbol Parameter Min. Typ. Max. Unit Conditions
AC Electrical Characteristics (Cont'd)
Transmitter (Cont'd) tKXH tKXL tKXCLK tBDTH tBITH tALH TX256kHz High Time TX256kHz Low Time TX256kHz Period BDT High Time BIT High Time ALARMIN High Time 488 12.5 15.6 1.95 1.95 3.9063 s s s ns s s
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . -65C to +150C
Magnetic Supplier Information: Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619) 674-8100 Fax. (619) 674-8262 Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402-0187 Tel. (702) 831-0140 Fax. (702) 831-3521
Rev. 2.02 6
XR-T6166
tRS RX2MHz tDRS time-slot tPW PCMOUT D0 D1 D2 D3 D4 D5 D6 D7 tRXD tDRH tRXL tRXH tRXCLK tRH
Figure 3. Receive Time-slot Timing
tRCKS S+R S-R tRCKP RXCKOUT
Figure 4. Extracted Clock Timing
tTS
tTXH
tTXL tTXCLK
tTH
TX2MHz
time-slot tDS PCMIN D0 D1 D2 D3 D4 D5 D6 D7 tDH
Figure 5. Transmit Time-slot Timing
tKXCLK tKXH Tr VIH 50% Clock VIL VIH 50% VIL 50% Tf tKXL
Figure 6. Clock Timing
Rev. 2.02 7
XR-T6166
SYSTEM DESCRIPTION Transmitter seventh and eighth data bits in each word to the same transmitter output. This function may be inhibited by setting ALARMIN (pin 16) high to transmit an alarm condition. Should skew occur between the TX2MHz and TX256kHz clocks signals, or during an adjustment of the timing of the time-slot signal, circuitry is included to delete or repeat complete words of data. This could happen, for example, when changing from one time-slot position to another. Outputs are provided to indicate when a data byte is inserted or deleted. A byte repetition or insertion occurs once if no new PCM data is received. The BIT flag (pin 18) is active during the transmission of inserted data. A byte repetition just occurs once. If no new PCM data is received, the T+R and T-R outputs stay high. A byte deletion occurs when the transmitter receives a new byte of data before the previous byte is transferred from the storage latch to the output register. Under this condition, the stored data is overwritten and the BDT flag (pin 11) is active. Receiver
Figure 1 shows the XR-T6166 transmitter section block diagram. The transmitter converts eight bit bursts or octets of 2.048Mbps serial data present in a PCM time-slot to a coded continuous 64kbps data stream. During operation, data input is controlled by external clock and time-slot signals, and the 64kbps data output is timed by an external 256kHz clock. Since the input and output rates may not be exactly equal because of slight clock rate differences, periodic slips can occur. Therefore, circuitry is included to delete or repeat octets, if necessary. Transmitter operation is as follows.
PCM data is applied to PCMIN (pin 19), a 2.048MHz local clock is applied to TX2MHz (pin 20), and a time-slot signal is applied through the time-slot multiplexer. This multiplexer allows the transmitter to be hard wired to two time-slot positions. A time-slot signal is applied to multiplexer inputs TS1T (pin 10) or TS2T (pin 12), and a time-slot select logic level is applied to TTSEL (pin 15). A high level at TTSEL selects TS1T while a low level enables TS2T. The time-slot is an envelope derived externally from TX2MHz that covers eight clock pulses. The rising edge of the time-slot signal should be made to coincide with the falling edge of TX2MHz. Eight bits of PCM data are clocked into the transmitter input register on the rising edge of TX2MHz while the selected time-slot signal is high. The input register data is then transferred to a storage latch. Transmission of 64kbps data is controlled by the 256kHz local clock that is applied to TX256kHz (pin 17). It is not necessary for this clock to be synchronized with any other signals that are applied to the transmitter. The output process begins by transferring data from the storage latch to the output shift register after transmission of the previous eight bits of data is complete. Four periods of TX256kHz are required to encode each data bit. A "logic 0" applied to PCMIN is coded as 0101 while a "logic 1" is coded as 0011. This data is output on either T+R (pin 13) or T-R (pin 14) according to the AMI (alternate mark inversion) coding rule. Note that the T+R and T-R outputs as well as the corresponding XR-T6164 transmitter inputs (TX+I/P, TX-I/P) are all active-low. Therefore, a "logic 0" is coded as a 1010 and a "logic 1" as a 1100 at the bipolar transmitter output as specified by CCITT G.703. Transmission of octet timing is performed by feeding the
Rev. 2.02 8
Figure 2 shows the block diagram of the XR-T6166 receiver section. The receiver converts coded continuous 64kbps data to eight bit bursts of 2.048Mbps serial data suitable for insertion in a PCM time-slot. During operation, data input is timed by a clock that is extracted from the input signal, while output is controlled by external locally supplied clock and time-slot signals. Since the data input and output rates may not be exactly equal, circuitry is included to delete or repeat eight bit data blocks, if necessary. Receiver operation is as follows.
A line interface chip such as the receive section of the XR-T6164 converts the encoded bipolar 64kbps signal to dual-rail active-low logic levels. These signals are applied to the XR-T6166 receiver S+R (pin 2) and S-R (pin 3) inputs. A 128kHz clock, which is derived from the received signal, is used to decode this data, and then to clock it into one of two storage registers. Two registers are used so that one may be receiving continuous data at 64kbps while the other is sending eight bit bursts at a 2.048Mbps rate to PCMOUT (pin 28) while the receiver time-slot signal is high. The time-slot is an envelope derived externally from RX2MHz (pin 5) that covers eight clock pulses. The rising edge of the time-slot signal should be made to coincide with the rising edge of RX2MHz. Eight bits of PCM data are clocked out of the receiver register on the rising edge of RX2MHz while the
XR-T6166
time-slot signal is high. A two input multiplexer at the time-slot input allows the receiver to be hard wired to two time-slot positions. time-slot signals are applied to TS1R (pin 23) and TS2R (pin 24) and the active time-slot is selected by RTSEL (pin 27). A high level applied to RTSEL selects TS1R and a low level selects TS2R. Data appearing at PCMOUT is framed by the read time-slot signal and is guaranteed glitch free. Recovery of the 128kHz timing signal is performed by a variable length counter which is clocked by the 2.048MHz signal applied to RXCK2MHz (pin 9). This clock is not required to be synchronized with any other signals that are applied to the XR-T6166. However, the RX2MHz clock may also be used for this function. Positive input data transitions are used to synchronize this counter with the data. If synchronization is lost, the counter length is shortened, and the clock recovery circuit enters a seek mode until a transition is found. This mode is identified by a high level at the CS output (pin 22). The extracted 128kHz signal is available at RXCKOUT (pin 7). Octet timing ensures that bit grouping is maintained when the data is converted from a 64kbps continuous stream to eight bit 2.048Mbps bursts. Bipolar violations are used to identify the last bit in each eight bit octet. In the absence of these violations, for example when receiving a transmitted alarm condition (transmitter ALARMIN is high), the circuit will continue to operate in synchronization with respect to the last received violation. During this time, the data present at PCMOUT is still correct as long as synchronization based on the last received violation is still valid, and the BLS input (pin 4) is held high. However, if BLS is low and an octet timing violation is not received, receiver output data is blanked by forcing PCMOUT to a high level. Also, if eight successive octet timing violations are not received, the ALARM output (pin 1) goes to a high level. A high level applied to the BLANK input (pin 6) will also force PCMOUT to an all-ones state. Slip control logic is included in the receiver to accommodate rate differences between input and output data. The 64kbps input rate is determined by the remote transmitter, while the PCMOUT rate is set by RX2MHz which is a local clock. If this clock is slow, an octet will be deleted periodically, while the last octet will be repeated under fast conditions. Octet timing is maintained during these operations. Outputs are provided to indicate when an octet is inserted or deleted. The BIR flag (pin 26) is high when PCMOUT data is repeated, and the BDR flag (pin 25) is high when the receiver deletes an octet. APPLICATION INFORMATION 64kbps Codirectional Interface
Figure 7 shows a codirectional interface circuit using the XR-T6166 with the XR-T6164 line interface. The XR-T6164 first converts the bipolar 64kbps transmit and receive signals to active-low TTL compatible data required by the XR-T6166. The XR-T6166 then performs the digital functions that are necessary to interface this 64kbps continuous data to a 2.048Mbps PCM time-slot. The 64kbps signals that have been attenuated and distorted by the twisted pair cable are transformer-coupled to the line side of the XR-T6164 as shown on the left side of Figure 7. A suggested transformer for both the input and output applications is the pulse type PE-65535.
The right side of Figure 7 shows the XR-T6164 LOS (Loss of Signal) output and the XR-T6166 digital inputs and outputs. All of these pins are TTL compatible. Please refer to the Pin Description section of this data sheet for detailed information about each signal.
Rev. 2.02 9
XR-T6166
T6164 LOS Output +5V +5V 1 28 26 25 7 22 4 5 23 time-slot 1 24 27 6 9 time-slot 2 time-slot Select Forces All Ones 2.048MHz Clock
XR-T6166
8 0.1F 0.1F 0.1F VDD
ALARM
Loss of TX Sync Data to PCM Bus Byte Repeat Flag Byte Delete Flag Recovered CLK CLK Seek Flag Blank O/P for Alarm 2.048MHz Clock
PCMOUT BIR BDR RXCKOUT
64kbps Data To Line TIP 1:2 480 RING
16
RX+I/P
9 V
1 2
RX-I/P I/P BIAS
13 15 V T CC C CC M DA C O N
3 R 12 X S+R A L 5 A R S-R M
Receive Side
2 S+R
CS BLS RX2MHz TS1R TS2R RTSEL BLANK
3
S-R
PE-65535 0.1F TTI-17147
64kbps Data To Line TIP 1:2 +5V
14 0.1F
PEAK CAP
RXCK2MHz
XR-T6164
BDT 11 18 19 20 10 12 15 17 16 Byte Delete Flag Byte Insert Flag Data from PCM Bus 2.048MHz Clock time-slot 1 time-slot 2 time-slot Select 256kHz Clock Inhibit Violations 10 TX+O/P G N D A 4 G N D D 7 21 VSS TX+I/P 11 13 T+R BIT
300
RING
300 0.1F
8
TX-O/P
TX-I/P
6
14
T-R
Transmit Side
PCMIN TX2MHz TS1T TS2T TTSEL
PE-65535 TTI-17147
TX256kHz ALARMIN
Figure 7. Typical Codirectional Application Circuit
Rev. 2.02 10
XR-T6166
Transmitter Code Conversion Step 2 - A binary 1 is coded as a 1100. Step 3 - A binary 0 is coded as a 1010. Step 4 - The binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks. Step 5 - The alternation in polarity of the blocks is violated every eighth block. The violation block marks the last bit in an octet.
Figure 8 shows the transmitter code conversion process that CCITT G.703 specifies for a 64kbps codirectional interface.
Step 1 - A 64kbps bit period is divided into four unit intervals.
Bit Number 64kbps data Steps 1-3
7 1
8 0
1 0
2 1
3 0
4 0
5 1
6 1
7 1
8 0
1 1
Step 4
Step 5
Octel Timing
Figure 8. Transmitter Code Conversion for a 64kbps Bipolar Line Signal
Rev. 2.02 11
IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII
Violation Violation
XR-T6166
Codirectional Interface Pulse Masks
Figure 9 and Figure 10 show the CCITT G.703 64kbps codirectional interface pulse masks for single and double pulses respectively of either polarity. Note that this mask
is for the pulse measured at the XR-T6164 transmitter output (application circuit shown in Figure 5) when terminated with a 120 resistor.
0.1 0.1
2.0
2.0
V 1.0
0.5
0
Figure 9. Mask for a Single Pulse
0.1 0.1
V 1.0
2.0
2.0
0.5
0
0.1 0.1
0.2
Figure 10. Mask for a Double Pulse
Rev. 2.02 12
I I I I I I I I
3.12s (3.9 -0.78) 3.51s (3.9 -0.39) 3.9s
0.1 0.1
0.2
4.29s (3.9 + 0.39) 6.5s (3.9 + 2.6) 7.8s (3.9 + 3.9)
I I I I I I I I
7.02s (7.8 - 0.78) 7.41s (7.8 - 0.39) 7.8s
8.19s (7.8 + 0.39) 10.4s (7.8 + 2.6) 11.7s (7.8 + 3.9)
XR-T6166
28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP)
Rev. 1.00
28
15 E1
1 D
14 E A2 A1
Seating Plane
A L B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.160 0.015 0.125 0.014 0.030 0.008 1.380 0.600 0.485 MAX 0.250 0.070 0.195 0.024 0.070 0.014 1.565 0.625 0.580
MILLIMETERS MIN 4.06 0.38 3.18 0.36 0.76 0.20 35.05 15.24 12.32 MAX 6.35 1.78 4.95 0.56 1.78 0.38 39.75 15.88 14.73
0.100 BSC 0.600 BSC 0.600 0.115 0.700 0.200
2.54 BSC 15.24 BSC 15.24 2.92 17.78 5.08 15
0 15 0 Note: The control dimension is the inch column
Rev. 2.02 13
XR-T6166
28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
D
28
15
E
H
14
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.697 0.291 MAX 0.104 0.012 0.020 0.013 0.713 0.299
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60
0.050 BSC 0.394 0.016 0.419 0.050
1.27 BSC 10.00 0.40 10.65 1.27
Rev. 2.02 14
XR-T6166 Notes
Rev. 2.02 15
XR-T6166
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1990 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.02 16

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